1. Field of the Disclosure
The present disclosure relates generally to polishing compositions, and methods for polishing semiconductor substrates using the compositions described herein. More particularly, the disclosure relates to chemical mechanical polishing compositions and methods for removing copper layers from a semiconductor substrate, where the compositions include synergistic combinations of surfactants.
2. Description of the Related Art
The process known as chemical-mechanical polishing (CMP) involves polishing different metal or non-metal layers on semiconductor wafers, using a polish pad and slurry. Copper is a commonly used material for forming interconnects in semiconductor manufacturing. Once a copper inlaid structure is formed by, for example, a damascene process, the isolated copper wires are made by polishing and clearing copper and barrier metal between the inlaid wires. Copper and barrier layer CMP involves polishing of copper and barrier layers. It is desired to polish the wafers at a high removal rate of material to enhance throughput, while still maintaining favorable wafer characteristics such as a low number of overall defects.
A typical copper CMP process consists of 3 process steps. First, the electro-plated copper overburden (up to 2 μm in thickness depending on technology node) is rapidly polished down at a relatively high down force, leaving some amount of copper until the deposition topography is fully planarized (see FIG. 1a). Throughput and planarization efficiency and low defects are key needs. The remaining copper overburden after full planarization during the first step is polished off at a lower down force, with a stop on the barrier layer (FIG. 1b).
In the above second polishing process, a phenomenon called dishing occurs, where the level of the top surface of the conductive film lowers. This is thought to be attributed to removal of the conductive films to an excessive degree, due to an excessively high ability of each of the first conventional polishing composition to polish the copper containing metal. The dishing reduces the cross-sectional area of the wiring, thereby causing an increase in wiring resistance. The dishing also impairs the flatness of the surface of a semiconductor device, thereby making it difficult to form multi-filmed wiring in the semiconductor device.
A goal in the CMP process is to clear all copper from the barrier metal, but achieve significantly low dishing on the inlaid copper wire, with very low defects and improved surface roughness. To this end, compounds functioning as dishing reducers (DR's) have been added to CMP compositions. Although this approach has met with some success, copper residue remaining on the wafer can be problematic when the concentration of dishing reducer is too high.